1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device in which a central processing unit or a logic circuit and a dynamic random access memory are mounted on a same semiconductor chip.
2. Description of the Prior Art
FIG. 21 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device having a dynamic random access memory (DRAM). In FIG. 21, the reference number 1 designates a semiconductor chip, 2 denotes the DRAM mounted on the semiconductor chip 1, and 3 indicates a wiring having a plurality of lines through which test patterns for the DRAM are transferred from an external device (omitted from FIG. 21) to the DRAM 2.
FIG. 22 is a block diagram showing a configuration of a conventional hybrid type semiconductor integrated circuit device in which a central processing unit (CPU) or a logic circuit and a DRAM are mounted on a same semiconductor chip. In FIG. 22, the reference number 4 designates a CPU or a logic circuit, 2 denotes a DRAM, and 5 indicates a wiring having a plurality of lines through which the CPU or the logic circuit 4 is electrically connected to the DRAM 2.
Next, a description will be given of the operation of the semiconductor integrated circuit device.
In the configuration of the conventional semiconductor integrated circuit device in which only the DRAM is mounted on the semiconductor chip 1, as shown in FIG. 21, when the test of the operation of the DRAM 2 is performed, test patterns provided from an external device are received through input terminals for test, and the received test patterns are then transferred to the DRAM 2 through the wiring 3.
After the completion of the test, the test patterns as test results are transferred from the DRAM 2 to the external device (omitted from FIG. 21) through the wiring 3 and output terminal for test. After this, the test patterns as the test result are compared with the original test patterns in order to check whether the DRAM 2 performs correctly or not.
FIG. 22 shows the configuration of the conventional semiconductor integrated circuit device of the hybrid type in which both the CPU or the logic circuit 4 and the DRAM 2 are mounted on the same semiconductor chip 1. This hybrid type semiconductor integrated circuit device is becoming one of the leading mainstreams of large scale hybrid integrated semiconductor circuit devices. By using this configuration of the semiconductor integrated circuit device shown in FIG. 22, because through the wiring 5 the CPU or the logic circuit 4 is directly connected to the DRAM 2, it is possible to avoid drawbacks such as occurrence of noise and signal transmission delay and increasing of a power consumption by an interface between a chip of the CPU or the logic circuit 4 and a chip of the DRAM 2 in other conventional semiconductor integrated circuit device.
However, in the configuration of the semiconductor integrated circuit device shown in FIG. 22, because the wiring 5 is formed between the CPU or the logic circuit 4 and the DRAM 2 to directly connect both them, because test patterns are not directly transferred from an external device to each of the CPU, or logic circuit 4 and the DRAM 2 directly, so that it is difficult to perform the test operation for each of them.
The outline of the discussion about the drawbacks of the conventional hybrid type semiconductor integrated circuit device is as follows:
Since the conventional semiconductor integrated circuit device has the configuration described above, because the wiring 5 is formed between the CPU or the logic circuit 4 and the DRAM 2 in the same semiconductor chip 1 in order to directly connect both them, so that test patterns are not directly transferred from an external device (not shown) to each of the CPU, or logic circuit 4 and the DRAM 2 and it is therefore difficult to perform the test operation for each of them.